This invention relates to apparatus for converting an electric analog signal into a corresponding digital signal, and more particularly to a high speed, high resolution analog/digital converter especially useful in a data acquisition system.
There are numerous devices available for converting an analog quantity into a corresponding digital quantity. One of the early A/D conversion techniques is the full parallel A/D converter in which an analog input signal to be converted is applied in parallel to a plurality of comparators, each comparator being referenced to a potential derived from a resistor chain comprising a plurality of equal value resistors which divide down a reference voltage so as to derive a comparator reference level for each possible quantization level. For any level of analog input signal, all comparators referenced to quantization levels below the input signal will be actuated, whereas those comparators referenced to levels above the input signal level will not be actuated. The outputs of all of the comparators are applied to a logic decoder which yields the corresponding parallel output digital signal. This type of converter is very fast, but it is obviously also very expensive since, for an n-bit converter it requires 2.sup.n -1 comparators and a relatively large and complex decoder. A 10-bit A/D converter will require 1,023 comparators. Other disadvantages are that the power dissipation is very high and it exhibits a large input capacitance due to the large number of comparators connected to the input terminal.
Another approach to the A/D conversion problem is the successive approximation analog/digital converter, the basic theory of which is described at pages 407-408 of the IEEE Transactions on Circuits and Systems, Vol. CAS-25 No. 7, July 1978. In a successive approximation register (SAR) method, the analog input voltage may be converted to a current and in each clock cycle this current is compared in a comparator with one bit of current from a digital/analog converter (DAC), starting with the most significant bit (MSB) of current. The comparator output represents the corresponding output bit of the A/D converter. Thus, an analog signal is converted into an n-bit digital signal in n clock cycles. The advantages of this approach are that the converter requires far less components, e.g. only one comparator, and that the power dissipation is much lower than the all-parallel method. A major disadvantage is that the conversion process is much slower in that it requires at least n clock cycles for an n-bit digital signal output.
A modification of the SAR method is the subranging A/D converter. The theory underlying this type of converter is described at pages 20-22 of the Analog-Digital Conversion Handbook, copyright 1964 by the Digital Equipment Corp. of Maynard, Mass. FIG. 18 of this handbook shows a subranging converter including a resistor chain, a series of comparators each with one input connected to the analog signal input terminal and second inputs connected to respective equally spaced tap points on the resistor chain. It also includes first and second DAC's connected respectively to the upper and lower ends of the resistor chain and a parallel decoder coupled to the outputs of the comparators. The subranging method operates by dividing the total input signal range into a number of subranges, selecting the appropriate subrange by means of the comparators and resistor chain, and then dividing this subrange into further subranges as before, and repeating the process until the desired resolution is achieved.
During a first clock cycle, the first DAC is set to the maximum voltage and the second DAC is set to zero. The outputs of the comparators indicate in which subrange the input signal falls, e.g. between the reference voltages applied to two adjacent comparators C.sub. k and C.sub.k+1. During the next clock cycle, the reference voltage for comparator C.sub.k is applied to the second DAC and the reference voltage for comparator C.sub.k+1 is applied to the first DAC so as to produce a second set of subranges between the values of the reference voltages for C.sub.k and C.sub.k+1. This is repeated until the desired resolution is obtained. A more sophisticated form of subranging A/D converter is shown in U.S. Pat. No. 3,298,014 in the name of B. W. Stephenson. A major disadvantage of these subranging A/D converters is that they require two digital/analog converters, which increases the size and cost of the apparatus, and presents additional problems in that the two DAC's must be accurately matched.